Advances over the years in the field of interconnection and device technology have played an important role in allowing continued scaling of the CMOS-based microelectronic products. In particular, scaling enabled improved device density and enhanced circuit performance. However, the increasing parasitic resistance in the nanometer regime is a key challenge in scaling of high performance CMOS devices. Series resistance components add to the degradation of intrinsic device current capability which directly impacts device performance. The continuing miniaturization of integrated circuits leads to increased parasitic resistance not only in the front-end-of-the-line (FEOL) level but also in the middle-end-of-the line (MOL) and back-end-of-the-line (BEOL) levels as decreased geometry results in increased resistivity of the interconnecting lines.
Increase of resistance of various device components has been a key parameter in predictive models of the ITRS roadmap. Up to the 65 nm Technology Node the MOL interconnection, i.e. contact level fabrication, has not been a key parasitic resistance contributor, but beyond this technology node predictions show that it will become an increasing issue. A comprehensive picture of contact level resistance scaling issues is depicted in FIG. 1. A simple predictive model shows that via resistance should increase by 1/k2 for every device generation, where k is the scaling factor. Due to the material limitations the resistance increase has been accelerating. Therefore, at 45 nm technology node innovative process solution based on liner thickness scaling had to be implemented to decrease the total plug resistance of the contact level build using W metallurgy. In addition to an increase in the nominal resistance value, process variability (3 sigma values) has also been increasing. As contact plug diameter shrinks below 50 nm any change in final critical dimension (CD) of a plug (diameter, height, side-wall angle) will result in large resistance variations. Such variations clearly degrade our ability to control yield and reliability of these vias beyond 45 nm technology node.
Tungsten is currently used for local wiring and for the contact level to the devices in microprocessors, ASICs and DRAMs. FIG. 2 shows how increasing contact resistance could result in 10% performance delay in F04 Inverter for 45 nm Technology Node if the current liner and CVD tungsten process is not optimized. More specifically, Curve A shows contact resistance increase with technology node for the current liner materials and tungsten fill processes. Curve B shows the F04 delay without the additional resistance contributed from contact plug. The curve C shows the actual F04 delay with the actual contact plug resistance. The difference between the latter two curves shows the contribution to the F04 delay from the contact plug resistance, which increases with technology node, and is predicted to reach 10% or more for 45 nm Technology Node if no additional innovative solutions are implemented to decrease plug resistance.
The most common metallization process for CA level includes deposition of I-PVD Ti layer for improved electrical contact to the silicide, a CVD TiN barrier protecting from corrosive W chemistry, followed by a CVD or ALD pulsed nucleation layer (“PNL”—doped W layer) followed by a CVD W fill. As CA dimensions are scaled the following issues become critical: inability to shrink a highly resistive liner and nucleation layers, lack of process providing W with lower resistivity values and good fill capability. The seam or voids in the contact plug becomes increasingly intolerable.
Therefore, providing contact metallurgy structures exhibiting reduced contact resistance by choosing lower resistivity materials to fill the plug, and minimizing center seam or voids for such structures is desirable.